1. Field of the Invention
The present invention relates to integrated circuit capacitor structures for MOS semiconductor processes.
2. State of the Art
In analog MOS designs, there is always a need for a high-precision, linear, bias-independent, low-impedance, high-unit-area capacitance, low-cost capacitor structure. The known MOS transistor-gate-to-well capacitor is readily available, therefore low-cost, and has high capacitance per unit area, but because of the nature of MOS capacitor, in which the silicon depletion layer modulates the capacitor, it is highly non-linear, bias-dependent, and therefore not high-precision. Current practice is to increase the doping level of the well near the silicon/oxide interface to reduce the depletion layer width, either by taking advantage of a special threshold voltage ("Vt") implant or having a "buried source/drain" implant prior to gate oxidation. A low Vt implant dosage (e.g., 10E12/cm2) is not sufficient to correct the linearity problem, and a buried source/drain (S/D) implant, which has a typical dosage of 10E15/cm2, results in a different, thicker MOS capacitor. Both of these options are generally not a part of a generic MOS process and add cost to manufacturing. What is needed, then, is a high-precision, linear MOS capacitor structure that can be produced as part of a generic MOS process. The present invention addresses this need.